Why Memory Per Chip Drives the Micron Investment Thesis

Memory per chip in Nvidia’s AI accelerators has jumped from 141 GB in the H200 to 288 GB in Blackwell Ultra, and the silicon underneath is what Micron is putting into high-volume production as HBM4 for Nvidia’s next platform. The progression is what compounds regardless of how many AI servers Nvidia ships. Most investors track the GPU shipment count, not the memory underneath.

That progression is the structural fact most retail accounts miss, and it shows up directly in the filings already in the public record. The SEC release that printed $9.30 billion in Q3 fiscal 2025 revenue, and the announcement that HBM4 is in high-volume production for Nvidia’s Vera Rubin platform, both anchor the same story. The numbers in those filings, the memory specifications on Nvidia’s product pages, and the supply discipline in the HBM market together describe the trade.

The One Number Most Investors Are Tracking Wrong

The Micron trade most investors describe runs on AI capex: hyperscaler spending on data centers, GPU unit shipments, and the assumption that more servers means more memory dollars for Micron. Wall Street earnings calls and analyst notes have spent the last two years on this framing, with revenue forecasts tied to AI capex projections. That logic captures part of the trade. Memory and compute scale at different rates inside AI accelerators, and the gap between them has been getting larger with every generation. The result is a second growth driver for Micron that does not depend on GPU units rising forever.

The relevant question is how much memory each new chip carries. Nvidia’s own product pages make the gap measurable. The H200 carries 141 GB of HBM3E at 4.8 TB/s, and Nvidia’s product page describes the chip as having “nearly double the capacity of the NVIDIA H100 GPU.”

Track memory per chip, and Micron’s growth runs on a different axis than GPU unit growth. That compounding is what explains why a memory name with the same business model as the last three decades is suddenly printing record data-center revenue.

From 141 GB to 288 GB in Two Generations

The H200 was the first GPU to ship with HBM3E, the higher-bandwidth revision of the high-bandwidth memory standard. Nvidia’s H200 product page lists the chip at 141 GB of HBM3E and 4.8 TB/s, with the capacity framed against its predecessor: “nearly double the capacity of the NVIDIA H100 GPU.” A generation later, the Blackwell family pushed the same die footprint toward larger stacks.

The Blackwell Ultra architecture, the latest member of the Blackwell family, ships with 288 GB of HBM3E per GPU, according to Nvidia’s technical blog, with memory bandwidth at 8 TB/s. The Blackwell Ultra blog post puts the figure at 3.6x the H100’s on-package memory and 2.4x its bandwidth, with the 3.35 TB/s figure for the H100 appearing in the same comparison. The change is not just a generational bump. Blackwell Ultra uses eight 12-Hi HBM stacks on a single package, an arrangement that requires the supplier to master both the base die and the through-silicon-via stack. That stacking is what the second column of the table captures, and why each new step costs more memory dollars per chip.

HBM4 Is Already in High-Volume Production

Micron moved HBM4 into high-volume production for Nvidia’s next Vera Rubin platform, the company said in a release on its investor relations site. HBM4 is the next generation of the high-bandwidth memory standard, with more dies stacked per package and faster signaling between them. Vera Rubin is the architecture Nvidia has positioned as the successor to Blackwell. Micron is in production on a generation the wider memory industry has not yet matched at scale.

The same generational rule that took the H200’s 141 GB to Blackwell Ultra’s 288 GB is set to apply to Vera Rubin. If Vera Rubin’s HBM4 stacks land at the higher die counts typical of the new standard, the per-package memory number moves again.

That is the next leg of the memory-per-chip trade. Micron being in high-volume production on HBM4 in the cycle that introduces that standard gives the company a chance to repeat the Blackwell Ultra step-up, with the cyclical risk that has defined the memory business for decades. The data on whether that happens arrives in the company’s quarterly filings.

Micron’s Run, In the Numbers It Has Filed

The HBM trade has already shown up in Micron’s filings. For the quarter ended May 29, 2025, Micron reported revenue of $9.30 billion, up from $8.05 billion the prior quarter and $6.81 billion a year earlier. The HBM line and the data-center segment drove the move: what the company called “all-time-high DRAM revenue,” “nearly 50% sequential growth in HBM revenue,” and a data-center segment that “more than doubled year-over-year and reached a quarterly record.” That was a quarterly record at the time, driven by the AI build-out Micron says it is now funding with manufacturing investments of its own.

“We are on track to deliver record revenue with solid profitability and free cash flow in fiscal 2025, while we make disciplined investments to build on our technology leadership and manufacturing excellence to satisfy growing AI-driven memory demand.”

Sanjay Mehrotra, Chairman, President and CEO of Micron Technology, gave the quote in the Q3 fiscal 2025 earnings release filed with the SEC on June 25, 2025. For the following quarter, Micron guided to revenue of $10.7 billion, plus or minus $300 million, with a GAAP gross margin of 41%, plus or minus one point. That guidance, issued in June 2025, has been overtaken by subsequent quarters. The trajectory, not the print, is what matters for the memory-per-chip thesis. The relevant line for the trade is HBM, not the consolidated revenue: memory dollars per chip compound faster than the rest of the business because HBM carries a pricing premium and a packaging complexity standard DRAM does not.

• Revenue: $9.30 billion for the quarter ended May 29, 2025 (vs. $8.05 billion the prior quarter, $6.81 billion a year earlier)
• HBM revenue: “nearly 50% sequential growth”
• Data-center revenue: “more than doubled year-over-year”
• Q4 FY2025 guidance: $10.7 billion ± $300 million revenue, 41% ± 1% GAAP gross margin
• Source: Micron Q3 fiscal 2025 earnings release, filed with the SEC, June 25, 2025

The Memory Cycle That Hasn’t Repeated Yet

Memory has historically been one of the most cyclical industries in technology: demand rises, manufacturers build, supply catches up, prices fall, margins compress. The pattern has played out repeatedly over the decades, and the lesson is that high-margin years invite capacity additions that eventually erase those margins. The current cycle has not yet repeated that script. AI demand is now large enough that it pulls a meaningful share of the global DRAM wafer base, leaving the broader market short, not long.

HBM is unusually hard to manufacture. The dies have to be stacked using through-silicon vias and bonded to a base logic die, with thermal and yield challenges commodity DRAM does not face. That complexity has kept HBM margins structurally above the rest of the memory market, and the bottleneck has been capacity, not pricing. If HBM stays a specialty product, the cycle behaves differently than the commodity DRAM cycles of the past.

The tightness is no longer confined to AI customers. DRAM prices have been rising across PCs and smartphones in 2026, with some supply partners warning of double-digit monthly price increases through the end of the year. Only a small number of suppliers can build HBM at the quality Nvidia and AMD require for their flagship accelerators, which keeps the market from being flooded even as more capacity comes online. The same DRAM and NAND that goes into AI accelerators is what gets bid up when AI customers place orders, and the rest of the market ends up competing for the same wafer output. That squeeze has reached the cheapest laptops on the market: Apple’s $599 MacBook Neo ships with 8GB, a constraint that traces to the same DRAM shortage driving HBM prices higher.

That is also where the cycle risk lives. If HBM matures into a commodity product with more competitors able to deliver at Nvidia’s spec, pricing converges toward the rest of DRAM. Memory is a story about capacity discipline as much as demand, and the companies that built too much in past cycles paid the price. Micron’s HBM4 mass production on time is what keeps the company on the right side of that bet, for now.

What Could Break the Memory-Per-Chip Trade

The thesis has a clean shape, and three things could unmake it. None is new to the memory industry, but each maps to a specific data point to watch.

First, HBM commoditization. The technology is hard, but a second or third supplier hitting Nvidia’s spec at scale would compress Micron’s premium and re-introduce the cycle. Second, AI capex moderation. If hyperscaler spending on data centers slows, the volume side of the trade weakens, even if memory per chip continues to climb. Third, a breakdown in the capacity discipline that has defined this cycle. Memory is a story about how much each supplier adds, and the cycle repeats when any one of them overbuilds.

The cleanest single number to track is the HBM line inside Micron’s quarterly filings, not the consolidated revenue. Investors will get the next read at the company’s next earnings release, due this quarter. Two filings are already in the public record: Micron’s Q3 fiscal 2025 earnings release, which printed $9.30 billion in revenue with HBM up nearly 50% sequentially, and the HBM4 high-volume production announcement on the company’s investor relations site. The next quarterly print will show whether the cycle is still holding its discipline.

Frequently Asked Questions

Why does memory per chip matter more than GPU unit sales for Micron?

Every Nvidia generation has packed more high-bandwidth memory onto the same die. The H200 ships with 141 GB of HBM3E; Blackwell Ultra carries 288 GB. That progression compounds regardless of how many accelerators Nvidia sells, and it is the line item Micron bills into.

What is HBM, and how is it different from regular DRAM?

HBM, or high-bandwidth memory, stacks multiple DRAM dies on top of a base logic die using through-silicon vias, which gives the GPU more memory bandwidth in a smaller area. The process is more complex than commodity DRAM, which has kept margins structurally higher for suppliers that can build it.

Who are Micron’s main competitors in HBM?

SK Hynix and Samsung are the other two primary suppliers of HBM to AI accelerator customers. The HBM market is concentrated in those three companies.

What is HBM4, and why does it matter for Micron’s stock?

HBM4 is the next generation of the high-bandwidth memory standard, with more dies per stack and faster signaling. Micron has moved HBM4 into high-volume production for Nvidia’s Vera Rubin platform, the company said in a release on its investor relations site, putting it in position to convert the next Nvidia generation into another step-up in data-center memory dollars.

Has the AI memory cycle peaked?

Not according to the data on file. Micron’s Q3 fiscal 2025 results showed HBM revenue growing “nearly 50%” sequentially, and the company guided to $10.7 billion in revenue for the following quarter. The risk is not current demand; it is whether the cycle keeps its discipline as more capacity comes online.

Disclaimer: This article is for informational purposes only and is not investment advice. Memory and semiconductor stocks carry significant cyclical risk, and past data-center revenue growth does not guarantee future results. Readers should consult a qualified financial professional before making investment decisions. Figures are accurate as of the publication date based on the sources cited.